Conventional serial data transceivers are operable for transmitting and receiving serial data on a communication medium. Serial data transmission is controlled by a transmit clock signal. The transceiver device receives as an input a potentially noisy external clock source, and produces the transmit clock signal in response to this external clock source. The noisy external clock source is typically cleaned up by applying thereto a narrow-band filtering operation. Conventional approaches implement the narrow-band filtering with an analog implementation, which requires large capacitors. Thus, such analog implementations either occupy a large amount of die area within the transceiver, or must be implemented externally of the transceiver, thereby necessitating additional components and associated costs.
Generation of the transmit clock signal is also affected by a phenomenon known as frequency pulling. Frequency pulling exhibits itself as a low frequency modulation of the phase-locked loop (PLL) clocks and the transmit clock signal by the nearby receive clock signal that has been recovered from the incoming serial data, which receive clock signal has a frequency very close to the frequencies of the PLL clocks and the transmit clock signal. The modulation frequency can be determined by the ppm offset of the respective clocks. The modulation amplitude depends on how and to what degree the two frequencies are coupled, e.g., through substrate and power supply. The problem of frequency pulling becomes more pronounced at higher levels of integration. In order to minimize coupling and crosstalk, some conventional approaches provide the receiver and transmitter as separate integrated circuits.
It is desirable in view of the foregoing to provide a serial data transceiver that can reduce frequency pulling and/or perform the aforementioned narrow-band filtering of an external clock source, while also maintaining acceptable levels of integration and cost.
Clock and Data Recovery (CDR) loops are used by conventional serial data transceivers to recover a clock from a received serial data stream and, subsequently, to recover and deserialize the received serial data. An example of such a conventional CDR loop, designated as CDR1, is illustrated diagrammatically in FIG. 1. A reference clock signal REF_CLK is input to a PLL 11, which in turn generates quadrature I and Q clocks with a frequency to within parts per million (ppm) of the data rate of the serial data RXD_i received at input 13. The I and Q clocks are then duty cycle-corrected (DCC) and phase interpolated (PI). The phase interpolated signal ICLK at 14 is interpolated to be coincident to the data transitions, and the phase interpolated signal QCLK at 16 is interpolated to be centered in the middle of the data eye.
A bang-bang phase detector (PD) uses the clock signals ICLK and QCLK to provide at 15 phase error information which can be interpreted in the digital domain. Therefore, the succeeding stages in the CDR loop, for example the decimator 17, the loop filter (LPF) and the phase interpolator PI, can be implemented with digital or mixed-signal techniques. The loop CDR1 outputs parallel data RD_i and the corresponding recovered clock.